Various techniques for avoiding loss of data written on, for example, a volatile memory in storage devices when power failures such as outages cause shutdown of the power supply have been proposed. For example, a technique for obtaining power for saving data from a volatile memory by using the capacitor discharge effect even during power supply shutdown caused by a power outage has been proposed.
The technique for avoiding loss of data involves, for example, a power outage process and a power recovery process which are executed in a computer system including a plurality of storage devices, such as a Redundant Arrays of Inexpensive Disks (RAID) device in order to avoid data loss caused by the occurrence of a power outage.
The power outage process is a process for saving or backing up data on a cache memory into a flash memory or the like (nonvolatile memory) when a power outage occurs. The power recovery process is a process involved in recovery from a power outage for restoring backup data on a flash memory to a cache memory to recover the state of the system to that before the occurrence of the power outage.
The power outage process and the power recovery process will now be briefly described with reference to the drawings. FIGS. 16 to 21 and FIGS. 22A to 22C are diagrams illustrating the related art. As illustrated in FIG. 16, a computer system of the related art includes a control enclosure (CE) having a control module (CM) for controlling the internal operation of the system, and a disk enclosure (DE) having a plurality of disks.
First, the power outage process will be described. Upon detection of the occurrence of a power outage, the CM is supplied with power from a super capacitor unit (SCU), and performs the power outage process by saving cache data on a cache memory into a flash memory and shutting down the power supply.
As illustrated in FIG. 17, the cache memory is divided into a system area, a table area, and a cache area. The table area contains device control information in the saved data, and the cache area contains user data in the saved data. When the device is booted up, the flash memory is initialized for the occurrence of a power outage, and contains no data. As illustrated in FIGS. 18 and 19, when the power outage process described above is executed, the data written on the table area and the cache area of the cache memory is saved into the flash memory. Since the system area is an area in which programs are written, no saving is required.
Next, the power recovery process will be described. When power is turned on because of recovery from the power outage, as illustrated in FIGS. 20 and 21, the CM copies or restores the cache data saved into the flash memory to the cache memory. After the cache data has been completely copied, as illustrated in FIGS. 22A to 22C, the CM performs an erasure process to erase all the blocks in the flash memory from the beginning. Accordingly, the power recovery process is executed. Japanese Laid-open Patent Publication No. 6-231053 is an example of the related art.
The technique for avoiding data loss using the power outage process and power recovery process described above has the following problem: When a power outage occurs once again during the erasure of the table area or cache area of the flash memory in the power recovery process, first, the erasure of all the blocks in the flash memory needs to be completed (see FIGS. 23A and 23B). Then, after the completion of the erasure of the flash memory, subsequently, the data on the cache memory is saved into the flash memory.
However, sufficient power to completely save the data from the cache memory to the flash memory may not necessarily be accumulated in the SCU after the completion of the erasure of the flash memory (see FIG. 23C). This may prevent the cache data from being completely saved into the flash memory and may cause loss of the latest data (table area) on the cache memory.
Furthermore, as illustrated in FIG. 24A, a technique for avoiding loss of latest data by assembling sequences so that the erasure of flash memories is shifted in timing between redundantly configured CMs has also been proposed. Even if a power outage occurs during the erasure of a flash memory controlled by one of the CMs, a flash memory controlled by the other CM is allowed to hold latest data. The loss of the latest data can thus be avoided. However, this technique is not applicable to a configuration including a single CM as illustrated in FIG. 24B. Such problems of the related art are illustrated in FIGS. 23A to 23C and FIGS. 24A and 24B.